1. Field of the Invention
The present invention relates to a liquid crystal display device with a color image display function, and in particular to an active-type liquid crystal display device.
2. Description of Related Art
Televisions and various other image display devices are being provided on a commercial base that has a liquid crystal display 5 to 50 cm in diagonal length in mass quantity through the progress in recent years in micro-fabrication, liquid crystal material, high-density packaging technology, and other such technologies. In addition, color displays can easily be obtained by forming an RGB color layer on one of the two glass substrates composing the liquid crystal panel. In particular, in a so-called active liquid crystal panel with a switching element inside each pixel, there is little cross-talk, the response rate is high, and images with a high contrast ratio are guaranteed.
For these liquid crystal displays (liquid crystal panels), the matrix organization generally comprises from 200 to 1200 scan lines and from around 300 to 1600 signal lines, but recently increases in screen size and definition are progressing simultaneously in response to the increase in display capacity.
FIG. 18 shows a prospective state of liquid crystal panel packaging in which electric signals are provided to an image display part using packaging means such as COG (Chip-On-Glass) in which a conductive adhesive is used to connect semiconductor integrated-circuit chips 3 for supplying a drive signal to electrode terminals 5 of the scan lines formed on one of the transparent insulating substrates composing a liquid crystal panel 1, for example a glass substrate 2, or TCP (Tape-Carrier-Package) for fixing a TCP film 4, to electrode terminals 6 of the signal lines using pressure and a suitable adhesive including a conductive medium using, for example, a thin polyimide-base plastic film with copper foil terminals plated with gold or solder as a base. Herein, both of these packaging methods are shown at the same time for convenience, but in actual practice, either method may be arbitrarily selected.
Wire paths connecting the interval between the pixels in the image display portion positioned nearly in the center of a liquid crystal panel 1 and terminals 5 and 6 of the scan line and the signal line are 7 and 8, and do not necessarily need to be constructed of the same conductive material as the electrode terminal groups 5 and 6. 9 is a color filter or an opposing glass substrate that is another transparent insulating substrate having transparent conductive opposing electrodes on its opposing side, which is common to all the liquid crystal cells.
FIG. 19 shows an equivalent circuit of an active-type liquid crystal display device with an insulating gate-type transistor 10 disposed as a switching element at each pixel. In the figure, 11 (7 in FIG. 18) is a scan line, 12 (8 in FIG. 18) is a signal line, 13 is a liquid crystal cell, and the liquid crystal cell 13 is treated as a capacitance element electrically. The elements drawn with solid lines are formed on the glass substrate 2, one of the glass substrates composing the liquid crystal panel 1, and opposing electrodes 14 drawn with dotted lines common to all the liquid crystal cells 13 are formed on the main surface of the other glass substrate 9 opposite the glass substrate 2. If the off resistance of the insulating gate-type transistor 10 or the resistance of the liquid crystal cell 13 is low, or if gradation in the displayed image is to be emphasized, circuitry means may be introduced such as adding an auxiliary storage capacitor 15 in parallel with the liquid crystal 13 as a load to increase the time constant thereof. 16 is a storage capacitor line forming a mother line common to the storage capacitors 15.
FIG. 20 shows a cross-sectional view of the essential part of an image display part of a liquid crystal display device. The two glass substrates 2 and 9 composing the liquid crystal panel 1 are formed separated by a specified distance of several μm by a spacer material (not illustrated) such as pillar-shaped resin spacers formed on the color filter 9, or plastic fibers or beads, and that gap is a closed space, sealed by a sealing material and a second end sealing material (neither of which are illustrated) made from an organic resin at the periphery of the glass substrate 9, and the gap is filled with liquid crystal 17.
To realize a color display, a thin organic film about 1 to 2 μm thick containing either a dye or pigment or both called a color layer 18 is deposited on the closed space side of the glass substrate 9, providing a color display function, in which case the glass substrate 9 may also be referred to by the name color filter (abbreviated as CF). Depending on the nature of the liquid crystal material 17, a polarization plate 19 is attached to the top of the glass substrate 9 or the bottom of the glass substrate 2 or both, so the liquid crystal panel 1 functions as an electro-optical element. TN (Twisted Nematic)-type liquid crystal material is currently used in most liquid crystal panels available commercially, and two polarization plates 19 are normally required. Although not illustrated, a back light source is disposed as a light source in the transmission-type liquid crystal panel, irradiating white light from below.
A thin polyimide-type resin film 20 about 0.1 μm thick, for example, formed on the two glass substrates 2 and 9 and in contact with the liquid crystal 17 is an alignment film for orientating liquid crystal molecules in a fixed direction. 21 is a drain electrode (wire) for connecting a drain of the insulating gate-type transistor 10 and a transparent conductive pixel electrode 22, and is often formed at the same time as a signal line (source line) 12. A semiconductor layer 23 is positioned between the signal line 12 and the drain electrode 21 and is described in further detail below. A thin Cr film layer 24 about 0.1 μm thick formed at the boundary of the adjacent color layer 18 on the color filter 9 is a light shield material for preventing external light from irradiating the semiconductor layer 23, the scan line 11, or the signal line 12. This is an established technology referred to as black matrix (abbreviated as BM).
Next, a description is given of the structure of an insulating gate-type transistor as a switching element and a manufacturing method thereof. Two types of insulating gate-type transistors are currently used commonly, one of which will be introduced as a conventional example and be referred to as an etch-stop type. FIG. 21 is a plan view of a unit pixel of an active substrate (semiconductor device for display devices) composing a conventional liquid crystal panel. Cross-section views of lines A-A′, B-B′ and C-C′ in FIG. 21(e) are shown in FIG. 22. The manufacturing process thereof is described briefly below.
First, as shown in FIG. 21(a) and FIG. 22(a), a first metal layer about 0.1 to 0.3 μm thick is deposited using an SPT (sputter) or other such vacuum film-depositing equipment on the main surface of the glass substrate 2, for example, product number 1737 manufactured by Coming, Inc., about 0.5 to 1.1 mm thick, as an insulating substrate with high-heat resistance, high chemical-resistance and high transparency, and the scan line 11 doubling as a gate electrode 11A and the storage capacitor line 16 are selectively formed using micro-fabrication technology. The material for the scan lines may be selected taking into consideration the combined properties of heat-resistance, chemical-resistance, hydrofluoric acid-resistance and conductance, though a metal or an alloy with a high heat resistance such as a Cr, Ta or MoW alloy, and a silicide thereof is generally used.
While using Al (aluminum) as the material for the scan lines is reasonable for lowering the resistance value of the scan lines in response to the larger screens and higher definition of liquid crystal panels, by itself, Al has a low heat resistance, so adding an oxide layer (Al2O3) in anodization of the Al surface or laminating with Cr, Ta or Mo or a silicide thereof, which are the said heat resistance metals, is currently the general technology in use. In other words, the scan lines 11 are constructed of one or more metal layers.
Next, a PCVD (Plasma-Chemical Vapor Deposition) equipment is used to successively deposit three thin film layers about 0.3, 0.05, and 0.1 μm thick, for example, comprising a first SiNx (silicon nitride) layer 30 composing a gate insulating layer, a first amorphous silicon (a-Si) layer 31 composing a channel for an insulating gate-type transistor including almost no impurities, and a second SiNx layer 32 composing an insulating layer for protecting the channel, over the entire surface of the glass substrate 2, and micro-fabrication technology is used to selectively leave the second SiNx layer above the gate electrode 11A narrower than the gate electrode 11A to form a protection layer 32D as shown in FIGS. 21(b) and 22(b), exposing the first amorphous silicon layer 31.
Continuing, the second amorphous silicon layer 33 including phosphorous, for example, as an impurity is deposited similarly about 0.05 μm thick, for example, over the entire surface using a PCVD equipment. Then, a thin film layer 34 of, for example, Ti, Cr, Mo or the like, is deposited as a heat-resistant metal layer about 0.1 μm thick, an Al thin film layer 35 about 0.3 μm thick is deposited as a low resistance wiring layer, and a Ti thin film layer, for example, is deposited as an intermediate conductive layer about 0.1 μm thick using an SPT or other vacuum film-depositing equipment as shown in FIG. 21(c) and FIG. 22(c). A drain electrode 21 of an insulating gate-type transistor and a signal line 12 doubling as a source electrode, comprising a laminate made of the three thin film layers 34A, 35A and 36A, which are source-drain materials, are selectively formed with micro-fabrication technology. This selective patterning is made by successively etching the Ti thin film layer 36, the Al thin film layer 35 and the Ti thin film layer 34 using a photosensitive resin pattern used in forming the source and drain wires as a mask, and then removing the second amorphous silicon layer 33 between the source and drain electrodes 12 and 21 to expose the second SiNx layer 32D as well as by removing the first amorphous silicon layer 31 in other regions to expose the gate insulating layer 30. The second SiNx layer 32D is thus present as a channel protective layer, and the etching of the second amorphous silicon layer 33 automatically ends, so this manufacturing method is referred to as etch-stopping.
Next, after removing the said photosensitive resin pattern, an SiNx layer about 0.3 μm thick is deposited over the entire surface of the glass substrate 2 similarly to the gate insulating layer as a transparent insulating layer using a PCVD equipment to form a passivation insulating layer 37, the passivation insulating layer 37 is selectively removed using micro-fabrication technology to form an opening 62 on the drain electrode 21, an opening 63 on the scan line 11 and an opening 64 on the signal line 12 outside an image display region, as shown in FIGS. 21(d) and 22(d), partially exposing the drain electrode 21, the scan line 11 and the signal line 12. An opening 65 is formed similarly on the electrode pattern bundled and in parallel with the storage capacitor line 16 to expose part of the storage capacitor line 16.
Finally, ITO (Indium-Tin-Oxide) or IZO (Indium-Zinc-Oxide), for example, is deposited as a transparent conductive layer about 0.1 to 0.2 μm thick using an SPT or other vacuum film-depositing equipment, and a pixel electrode 22 is selectively formed using micro-fabrication technology on the passivation insulating layer 37 containing the opening 62 to complete the active substrate 2 as shown in FIGS. 21(e) and 22(e). The portion of the scan line 11 exposed in the opening 63 may be used as the electrode terminal 5, and the portion of the signal line 12 exposed in the opening 64 as the electrode terminal 6, and the electrode terminals 5A and 6A made from ITO on the passivation insulating layer 37 containing the openings 63 and 64 may be selectively formed as illustrated, but a transparent conductive short line 40 is ordinarily formed at the same time connected between the electrode terminals 5A and 6A. The reason for this is so a high resistance can be made as a measure against static electricity by forming the interval between the electrode terminals 5A and 6A and the short wire 40 into a long, narrow striped forms to increase the resistance (not illustrated). Similarly, an electrode terminal is formed in the storage capacitor line 16 containing the opening 65, though a number thereof is not provided.
If wiring resistance of the signal wire 12 is not a problem, a low resistance wire layer 35 made from Al is not necessarily required, in which case it is possible to simplify the layers of the source and drain wires 12 and 21 by selecting a heat-resistant metal material such as Cr, Ta or Mo. Ensuring an electrical connection with the second amorphous silicon layer using a heat-resistant metal layer is thus more important for the source and drain wires; the heat resistance of an insulating gate-type transistor is described in detail in Unexamined Patent Application Number H 7-74368 [i.e., 1995-74368] as an example of prior art. A region 50 (a right-slanting oblique portion) over which the storage capacitor line 16 and the drain electrode 21 are superimposed in a planar manner via the gate insulating layer 30 in FIG. 21(c) forms a storage capacitor 15, though a detailed description is omitted here.
A detailed history of the five-mask process described above is omitted, but this is obtained as the result of streamlining the semiconductor layer islanding process and decreasing the number of contacts formation processes by one. Photomasking, which initially required seven to eight processes, has been reduced to the current five layers by the introduction of dry etching technology which greatly contributes to the decreasing process costs. It is a well-known target of development that lowering the process cost in the manufacture of the active substrate and the material cost in the panel assembly and module packaging processes is effective in lowering the production costs of liquid crystal display devices. To lower process costs, either processes may be eliminated to make the process shorter, or inexpensive process development or process replacement to inexpensive process is available. Here, a four-mask process resulting in an active substrate with four photomasks is described as an example of eliminating processes. The photo-etching process is eliminated by introducing half-tone exposure technology. FIG. 23 shows a plan view of a unit pixel in an active substrate corresponding to the four-mask process. The cross-section views of lines A-A′, B-B′ and C-C′ in FIG. 23(e) are shown in FIG. 24. As already mentioned, two types of insulating gate-type transistors are commonly in use currently. Here, a channel etch type insulating gate-type transistor is used.
First, as shown in FIGS. 23(a) and 24(a), a first metal layer about 0.1 to 0.3 μm thick is deposited on the main surface of a glass substrate 2 using an SPT or other vacuum film-depositing equipment similar to that done in the five-mask process, and a storage capacitor line 16 and a scan line 11 doubling as a gate electrode 11A are selectively formed with micro-fabrication technology.
Next, three thin film layers comprising a first SiNx layer 30 composing a gate insulating layer, a first amorphous silicon layer 31 composing a channel for an insulating gate-type transistor including hardly any impurities, and a second amorphous silicon layer 33 composing a source and drain for an insulating gate-type transistor including impurities are successively deposited about 0.3 to 0.2 to 0.05 μm, for example, over the entire surface of the glass substrate 2 using a PCVD equipment. Next, a Ti thin film layer 34, for example, as a heat-resistant metal layer about 0.1 μm thick, an Al thin film layer 35 as a low resistance wire layer about 0.3 μm thick, and a Ti thin film layer, for example, as an intermediate conductive layer about 0.3 μm thick, that is, source-drain wire material is successively deposited using an SPT or other vacuum film-depositing equipment, and a drain electrode 21 for an insulating gate-type transistor and a signal line 12 doubling as a source electrode are selectively formed using micro-fabrication technology. In this selective patterning, forming photosensitive resin patterns 80A and 80B thinner than the 3 μm of the source-drain wire formation regions 80A (12) and 80A (21) with the channel formation region 80B (oblique portion) between the source and drain 1.5 μm thick, for example, as shown in FIGS. 23(b) and 24(b) using half-tone exposure technology is a major feature.
For such photosensitive resin patterns 80A and 80B, a positive photosensitive resin is ordinarily used in the production of substrates for liquid crystal display devices, so a black, that is, a thin Cr film is formed for a source-drain wire formation region 80A, a gray (gray tone) line and space Cr pattern is formed with a width of 0.5 to 1 μm, for example, for a channel region 80B, and for other regions, a photomask may be used to make them white, that is, remove the thin Cr film. It is possible to transmit about half of the photomask radiant light from a lamp source because the fine lines and spaces are not resolved due to the lack of resolution with an aligner, so the photosensitive resin patterns 80A and 80B may be obtained in the gray region having a cross-section form such as that shown in FIG. 24(b) corresponding to the residual film properties of the positive type photosensitive resin. By depositing an MoSi2 thin film having different thickness from Cr thin film, for example, rather than a Cr thin film slit in the gray region, a photomask with an equivalent function may be obtained.
After successively etching the Ti thin film layer 36, the Al thin film layer 35, the Ti thin film layer 34, the second amorphous silicon layer 33 and the first amorphous silicon layer 31 using the aforementioned photosensitive resin patterns 80A and 80B as masks to expose the gate insulating layer 30 as shown in FIG. 24(b), the photosensitive resin patterns 80A and 80B are decreased at least 1.5 μm with ashing means such as oxygen plasma, eliminating the photosensitive resin pattern 80B to expose the channel region, and leaving the reduced photosensitive resin patterns 80C (12) and 80C (21) only on the source-drain wires formation region as shown in FIGS. 23(c) and 24(c). The Ti thin film layer, Al thin film layer, Ti thin film layer, second amorphous silicon layer 33A, and first amorphous silicon layer 31A between the source-drain wires (the channel formation region) are successively etched using the thinned photosensitive resin patterns 80C (12) and 80C (21) as masks again, and then the first amorphous silicon layer 31A is etched leaving around 0.05 to 0.1 μm. After the source and drain wire materials are etched, the first amorphous silicon layer 31A is etched leaving around 0.05 to 0.1 μm, thereby forming the source-drain wires, so the insulating gate-type transistor obtained with such a manufacturing method is referred to as a channel etch. The resist pattern 80A is reduced so as to be converted to 80C in the said plasma treatment, so it is desirable to strengthen the anisotropicity to suppress changes in the pattern dimensions. In further detail, RIE (Reactive Ion Etching) oxygen plasma treatment is desirable, and ICP (Inductive Coupled Plasma), or TCP (Transfer Coupled Plasma) oxygen plasma treatment with a higher density plasma source is even more desirable.
After removing the said photosensitive resin patterns 80C (12) and 80C (21), a second SiNx layer about 0.3 μm thick is deposited as a transparent insulating layer over the entire surface of the glass substrate 2 to make a passivation insulating layer 37 as shown in FIGS. 23(d) and 24(d) similar to the five-mask process; openings 62, 63 and 64 are formed on the drain electrode 12, on the scan line 11 and on the signal line 12 outside an image display region, respectively; the gate insulating layer 30 and the passivation insulating layer 37 in the opening 63 are removed to expose part of the scan line in the opening 63; and the passivation insulating layer 37 in the openings 62 and 64 is removed to expose part of the drain electrode 21 in the opening 62 and part of the signal line in the opening 64.
Finally, ITO or IZO, for example, is deposited as a transparent conductive layer about 0.1 to 0.2 μm thick using an SPT or other vacuum film-depositing equipment, and a pixel electrode 22 containing the opening 62 is selectively formed on the passivation insulating layer 37 using micro-fabrication technology to complete the active substrate 2 as shown in FIGS. 23(e) and 24(e). For the electrode terminals, transparent conductive electrode terminals 5A and 6A made from ITO are selectively formed on the passivation insulating layer 37 containing the openings 63 and 64.